1 publication

• Published Subscription Review Article 2 Apr 2026

  Design and Analysis of Low-Power CMOS Inverter Chains for High-Speed Digital Circuits

  By Anupriya V, Hemalatha R, Kaviya Sri A, Madhumitha P, Nanthitha S

  Abstract: This report briefly explains the design process, structure, and evaluation of a CMOS inverter designed using a 45 nm technology process with a focus on its propagation delay and power consumption. Moreover, the CMOS inverter design will be created using the Cadence Virtuoso design environment, along with a post-layout analysis of the design. Performance evaluation of the designed circuit will be carried out through the execution of a transient analysis …

  Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 40–57 Read article →