1 publication

• Published Subscription 1 Mar 2019

  Implementation and Analysis of 32-bit pipelined RISC Processor Architecture

  By P. Indira, M. Kamaraju

  Abstract: Pipelining is an implementation technique, in which parallel operations are performed for several instructions simultaneously, to save time, enhance speed and for better utilization of hardware units. In this paper, 32-bit, 5-stage RISC processor is used to tag the pipeline stages to obtain the optimized results. The architecture of the processor containing several elements reduces the debugs and upholds the high performance through critical functions. When compared to our closest …

  Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 1–14 Read article →