1 publication

• Published Subscription 4 May 2022

  Design and Implementation of Array for Scaling Power and Area in 4t SRAM Cell

  By A. Vijayaprabhu, Kalaivani SK, Muthamizhan M., Vijayaraghavan. N

  Abstract: In this article in order to reduce the power and area of the Static Random-Access Memory (SRAM) array while maintaining the competitive performance. By using the CMOS technology, the design structure is made to for desired configuration of SRAM array by utilizing the SRAM cell and six-transistor (6T), In order to reduce the number of switches for enhancing performance working with the deep submicron of values 130nm, 90nm and 65nm …

  Published in Journal of Semiconductor Devices and Circuits · Vol. 9, Issue 1, 2022 · pp. 29–33 Read article →