1 publication

• Published Subscription 24 May 2017

  Low-Power and Area-Efficient N-Bit Carry-Select Adder

  By k Tejasvi, G Shyamkishore

  Abstract: Design of High Efficiency Carry Select Adder Using SQRT Technique presents many opportunities for increasing the speed and reducing the area of any data processor. Only Carry Select Adder (CSLA) is the fastest adders which are used in many data-processing processors to perform fast arithmetic operation. From the structure of the CSLA, it is clear that there is scope for reducing the area and delay in the CSLA. In this …

  Published in Journal Of Network security · Vol. 5, Issue 1, 2017 · pp. 22–27 Read article →