1 publication

• Published Subscription 9 Aug 2019

  A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit

  By M. Hulkey, H. Upadhyay, K. Sujhatha

  Abstract: Modified constant delay logic style and clocked logic style is defined by comparing their result. In this paper, a design technique has been proposed which reduces the power dissipation. The design and implementation of full adder and ripple carry adder with constant delay logic. The leakage power has become a serious concern in CMOS technologies that has been solved by the MCD and clocked logic style. Constant delay logic style …

  Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 1–5 Read article →