1 publication

• Published Subscription 9 Aug 2019

  A Unified Ultra-Low Power Architecture of Probabilistic Adder Based on GDI Technique

  By B S Patro, srinibasa padhy, monica swain, J K Das

  Abstract: In the present arena of technology scaling, the power consumption in the deep submicron technology plays a pivotal role as the transistor counts increases dramatically. Therefore, the need of the hour is to focus on power dissipation. The rate of occurrences of errors in the present VLSI scenarios has become higher and inevitable, and is increasing along with technology scaling. Eradicating all the errors is a cumbersome task; still a …

  Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 45–55 Read article →