1 publication

• Published Subscription 20 Apr 2019

  Implementation of Different Low Power Techniques on CMOS Inverter and NAND Circuits

  By Karishma Yadav, Vandana Khanna, Gaurav Shingwani, Ishita Ishita

  Abstract: The growth in technology has increased the usage of additional components on a single chip. This increased number of components on a single chip increases the significant amount of power dissipation and this causes the major challenge for the today’s circuit designers. There are several techniques in VLSI field which help to reduce power dissipations. This paper has analytical analysis of different low power techniques on CMOS inverter and NAND …

  Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 38–43 Read article →