2 publications

• Published Subscription 9 Aug 2019

  A Review for Power Optimization in MOS Devices using Different Logic Styles

  By M. Hulkey, H. Upadhyay, K. Sujatha

  Abstract: This paper presents power optimization in MOS devices by using different logic styles which is helpful for increasing high speed application. The simulation process can be done in different CMOS technologies and performance parameter of power is compared for different logic styles. Full adder and ripple carry adder are mostly used to define different logics to optimize the power. Constant logic style provides the low power and different logic style …

  Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 16–20 Read article →

• Published Subscription 9 Aug 2019

  A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit

  By M. Hulkey, H. Upadhyay, K. Sujhatha

  Abstract: Modified constant delay logic style and clocked logic style is defined by comparing their result. In this paper, a design technique has been proposed which reduces the power dissipation. The design and implementation of full adder and ripple carry adder with constant delay logic. The leakage power has become a serious concern in CMOS technologies that has been solved by the MCD and clocked logic style. Constant delay logic style …

  Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 1–5 Read article →