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Impact of Xilinx ISE Design Suite’s MAP and Generate Programming Optimization Settings on FPGAs Bitstream SizeBy Pravin N. Matte, Dilip D. Shah
Abstract: AbstractIn SRAM based FPGA configuration bitstream resides in configuration memory. Bitstream contains information of CLBs, IOBs and logic interconnects. With increase in complexity of design, size of bitstream increases. Hence if size of bitstream is reduced, less configuration memory required. CAD tools used in FPGA based design has different settings which affects logic capacity, performance speed, resource utilization, power consumption, area required for placing designs etc. In this paper, we …
Published in Journal of Electronic Design Technology · Vol. 9, Issue 1, 2018 · pp. 1–8 Read article →