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• Published Subscription 25 Jan 2021

  Design and Simulation of Ternary Gates Using Fin-FET

  By Mahesh Dhoot, Digvijay Runde, Satish Narkhede

  Abstract: In recent years, digital communication system has becomes more popular. But the on-chip interconnections have become a major problem as more and more modules are packed into a chip by reducing the gate size. As the gate size is reduced further the complexities in the circuit increases. Binary logic circuit dissipates a lot of energy, increase processing time, and causes coupling effect. In the Ternary logic system, there are three …

  Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 3, 2015 · pp. 4–18 Read article →