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• Published Subscription 22 Jan 2021

  Simulation Study of Process Variations in Double Gate Junctionless Field-Effect Transistors

  By Arindam Deb Singha, Arun Kumar Chatterjee

  Abstract: This work discusses the process variations in symmetrical double-gate (DG) junctionless (JL) field-effect transistors (FETs) by device simulation. Output I-V characteristics along with subthreshold slope increase, DIBL variations with drain voltage and threshold voltage shift variations are systematically analyzed with the general variability issues including oxide thickness, channel thickness and doping concentration. Potential distribution in the body channel region is also analyzed. Optimum values of the variability factors are considered …

  Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 2, 2015 · pp. 18–27 Read article →