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• Published Subscription 15 Feb 2019

  A Novel Efficient VLSI Architecture for Matrix Multiplication using Compressor-based Multiplier

  By Kirti Sharma, Anushree .

  Abstract: Due to advancement of new technology in the field of VLSI, there is an increasing demand of high speed processor. Matrix multiplication is highly used in different types of computations. Speed of processor greatly depends on its multiplier (used in matrix multiplication) performance. Due to which high speed multiplier architecture become important. Several multiplication techniques have been developed to increase the efficiency of the multiplier. These techniques help in reducing …

  Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 23–28 Read article →