1 publication

• Published Subscription 16 Jul 2018

  Design and Performance Analysis of Full Adder Cell using FinFET Technique at 32nm Technology

  By Saurabh Kumawat, Purushottam Kumawat, Akanksha Choudhary

  Abstract: AbstractIn this paper, discussed is the comparative analysis of complementary MOS (CMOS) and dual gate-FinFET (fin shaped field effect transistor) based full adder cell design. To reduce the average power, average current and maximum current of 1-bit full adder circuit a new high DG-FinFET technique is presented. Use of double-gate FinFET technology provides low leakage and high performance operation. For MOSFET transistor model, a predictive technology model (PTM) BSIM4 and …

  Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 1–8 Read article →