Multi-Valued Logic (MVL)

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• Published Subscription Review Article 2 Apr 2026

  High Performance Multi-Valued Logic (MVL)Gate Design Using FinFET

  By V. Anand Vardhan, G. Naga Chaitanya, V. Bhargav Shankar, Harika Pangam, Ch.Sridevi, M.M.Vara Lakshmi

  Abstract: CMOS scaling faces challenges such as leakage, power dissipation, and short channel effects. Multi-Valued Logic (MVL) offers higher information density and reduced interconnections. This work presents a FinFET-based MVL gate design that improves electrostatic control, switching speed, and reliability. Simulation results confirm reduced leakage power and enhanced performance compared to conventional logic. The proposed architecture demonstrates scalability for advanced technology nodes. It also shows potential for low-power applications in portable …

  Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 34–45 Read article →