mirror-symmetric topology
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Mirror-Symmetric NoC Topologies for 64-Core Arrays: Investigating Latency and Energy Trade-offs versus Mesh and Torus Interconnects for Block-Level Matrix Multiplication Workloads
Abstract: Modern chip multiprocessors increasingly rely on many-core arrays to accelerate dense linear algebra kernels such as block-level general matrix multiplication (GEMM), where inter-tile communication often rivals computation cost. Network-on-Chip (NoC) topology therefore strongly influences overall latency and energy efficiency. This work proposes a mirror-symmetric NoC topology for 64-core arrays, in which long-range bypass links are added about a central reflective axis to shorten paths between symmetric core partitions that frequently …
Published in Journal of Operating Systems Development & Trends · Vol. 13, Issue 2, 2026 · pp. 35–44 Read article