1 publication

• Published Subscription Review Article 10 Sep 2024

  Design And Optimization Of High-Speed Array Multiplier

  By Vaishnavi M. N, K.B Ramesh

  Abstract: An array multiplier is a digital circuit used for the rapid multiplication of binary numbers. It employs an array of logic gates to generate partial products concurrently, significantly enhancing speed. The array structure divides the multiplication task into smaller, parallel processes, allowing for efficient parallel processing of multiple bits. Each cell within the array manages specific bit-level multiplications, and their results are summed to produce the final product. This parallel …

  Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 Read article →