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Design and Analysis of Different Delay Lines with Different Performance ParametersBy Pankaj Prajapati, Ratnesh Pandey
Abstract: In this article, an analysis of different delay lines (DL) based on CMOS (Complementary metal–oxide–semiconductor) architecture has been done. Comparison has been made on these delay lines in terms of propagation delay, power dissipation, area, and power delay product.After the analysis of those performance parameters, the tradeoff has been made for better performance of delay lines. There are 10 stage tapped delay lines which are used. A process used for …
Published in Journal of Instrumentation Technology & Innovations · Vol. 7, Issue 1, 2017 · pp. 1–6 Read article →