1 publication

• Published Subscription 3 Dec 2015

  Efficient Design of Pseudo-Random Pattern Generator with High Fault Coverage

  By Gargi Kaushik, Dinesh Chandra, Sangeeta Mangesh

  Abstract: In this paper a comparative analysis of various test pattern generators is done in terms of power consumed .Testing is a crucial process in VLSI (Very-large-scale integration), not only it ensures proper functioning of the chip ,it also helps identify the common faults that occur as a part of VLSI fabrication. However, the power consumed during the testing process is nearly 40% higher than normal circuit operation. Various test pattern …

  Published in Journal of Microelectronics and Solid State Devices · Vol. 1, Issue 1, 2015 · pp. 21–25 Read article →