Low-Power Reconfigurable Digital Filter Design Using FPGA for IoT Edge Devices - Bhima Shankar Kumbhar; Rohidas Kendre; Vaibhav Godase (International Journal of VLSI Circuit Design & Technology, 2025)
The rapid evolution of the Internet of Things (IoT) has led to an exponential increase in the deployment of edge devices that continuously process real-time sensor data under strict power, latency, and computational constraints. Digital filtering remains a critical operation in these devices, supporting tasks such as noise removal, data conditioning, and feature extraction for intelligent decision-making. However, conventional filter implementations on microcontrollers or fixed digital signal processors often struggle to meet the low-power and high-performance requirements of battery-operated IoT systems. To address these limitations, this paper presents a low-power reconfigurable finite impulse response (FIR) digital filter architecture optimized for FPGA-based edge environments. The proposed design leverages distributed arithmetic to eliminate the use of power-hungry multipliers, incorporates coefficient symmetry and pipelining to minimize logic activity, and integrates dynamic partial reconfiguration to support real-time adaptability without requiring full hardware resynthesis. The architecture is implemented and evaluated on a Xilinx Artix-7 FPGA platform using real- world sensor inputs from temperature and vibration modules. Experimental results demonstrate a 42.7 percent reduction in total power consumption, a 31.4 percent reduction in LUT utilization, and an 18.3 percent improvement in maximum operating frequency compared to conventional multiplier-based FIR designs. The reconfiguration mechanism enables seamless modification of filter order and coefficients, significantly enhancing flexibility for dynamic IoT environments. These results confirm that the proposed architecture offers a robust, energy-efficient, and scalable solution for next-generation IoT edge devices requiring real-time digital signal processing.
Keywords: FPGA; IoT edge devices; Low-power design; distributed arithmetic; partial reconfiguration; reconfigurable digital filter; signal processing architecture