Design and Implementation of Low Power and Area Efficient Sub Threshold Level Shifter Using 16 nm CMOS Technology - J. Spandana; L. Jagadeesh Naik (International Journal of VLSI Circuit Design & Technology, 2023)
An efficient method of modifying subthreshold voltages is proposed here. As an alternative to static power dissipation, the suggested design allows for charging of internal nodes through VDDH. The force of the pull-down mechanism may be increased by connecting a second auxiliary circuit. The transition energy for input frequencies between 1 and 5 MHz is 84 fJ, the propagation delay is 46 ns, the dynamic power dissipation is 0.3 mW, and the static power dissipation is 23 mW, according to post-layout simulations of level shifters in 16 nm CMOS technology. Silicon has a precise area of 60.6902 microsquare meters, which is an intriguing statistic.
Keywords: CMOS; CPU; auxiliary circuit; logic circuits; power dissipation